1. Field of the Invention
This invention relates to a semiconductor device, a wiring board and a method of making the wiring board and, in particular, to a semiconductor device such as BGA (Ball Grid Array) or CSP (Chip Size/Scale Package) that uses external connection terminals of tin-zinc alloy etc.
2. Description of the Related Art
Conventionally, semiconductor devices called BGA or CSP are structured such that a semiconductor chip is mounted on a wiring board composed of an insulating substrate with wirings formed thereon.
For example, in a BOA type semiconductor device, as shown in FIGS. 1A and 1B, a semiconductor chip 3 is mounted through adhesive 8 on a wiring board composed of an insulating substrate 1 and wirings 2 formed thereon. The wirings 2 of wiring board are electrically connected through bonding wires 9 with external electrodes 301 of the semiconductor chip 3.
Also, as shown in FIGS. 1B and 2, the insulating substrate 1 of wiring board is provided with openings 101 for placing external connection terminals 4, and part of wiring 2 is disposed shutting one end of the opening 101. The external connection terminal 4 is electrically connected with the wiring 2 in the opening 101.
Also, as shown in FIG. 2, thin film conductor 5 is provided on the surface of wiring 2 and at the bottom of opening 101. In case of BGA type semiconductor device shown in FIGS. 1A and 1B, the thin film conductor 5 is frequently of gold plating or gold plating with nickel plating base layer so as to give a good connectivity with bonding wire 9.
As shown in FIG. 2, the thin film conductor 5 is frequently disposed at the bottom of opening 101. Thus, the wiring 2 is electrically connected through the thin film conductor 5 (gold plating) with the external connection terminal 4. The external connection terminal 4 is of an alloy including gold, e.g. tin-zinc alloy. Thereby, intermetallic compound layer 7 between gold and tin-zinc alloy is generated at the interface of external connection terminal 4 and thin film conductor 5.
A method of making the wiring board used for the semiconductor device will be described below. First, as shown in FIG. 3A, conductor film 2′ of copper foil is sticked onto the insulating substrate 1 in which openings 101 are formed by punching with a metal mold (punching mold). Alternatively, after the conductor film 2′ is sticked to the insulating substrate 1, openings 101 nay be formed in the insulating substrate 1 by radiating laser light such as carbon dioxide layer.
Next, the conductor film 2′ is etched to form wirings 2 as shown in FIG. 3B. The wirings 2 are formed by using the additive method or subtractive method.
Then, as shown in FIG. 3C, thin film conductor 5 of gold plating with nickel plating base layer is formed on the surface of wiring 2 and at the bottom of opening 101.
A method of making the semiconductor device using the wiring board thus obtained will be described below. As shown in FIG. 1B, the semiconductor chip 3 is sticked through adhesive 8 onto the wiring board. After the external electrode 301 of semiconductor chip 3 is electrically connected through bonding wire 9 with the wiring 2 of wiring board, the semiconductor chip 3 and the peripherals are sealed with insulation 10. Then, the external connection terminal 4 is placed at the opening 101 disposed in the insulating substrate 1.
In forming the external connection terminal 4, generally, as shown in FIG. 4, solder ball 4′ of tin-zinc alloy is at opening 101 in the insulating substrate 1 and then is ref lowed by heating. At that time, the solder melted flows into the opening 101, contacting thin film conductor 5 (gold plating) provided at the bottom of the opening 101. Thereby, as shown in FIG. 2, intermetallic compound layer 7′ between gold and tin-zinc alloy is formed to connect (join) the external connection terminal 4.
In recent years, due to the miniaturization and high-density arrangement of external connection terminal 4 formed in semiconductor device, the aspect ratio of opening 101, i.e., a ratio of depth and diameter of opening 101 is increasing. Therefore, there is a problem that a defective connection is likely to occur between external connection terminal 4 and thin film conductor 5 (wiring 2) since the distance from solder ball 4′ on the opening 101 to thin film conductor 5 at the bottom of the opening 101 is increased.
On the other hand, when the aspect ratio of opening 101 is increased, the amount of solder flown into the opening 101 in reflowing the solder ball 4′ increases. Therefore, there is also a problem that the external connection terminal 4 is likely to have a defective shape.
In order to prevent such problems as defective connection between external connection terminal 4 and thin film conductor 5 (wiring 2) and defective shape in external connection terminal 4, as shown in FIG. 5, embedded conductor layer 6, is formed in opening 101 by copper chemical gilding and then thin film conductor 5 is formed thereon (See, for example, Japanese patent application laid-open No.10-41356).
In the wiring board that embedded conductor layer 6′ is formed in opening 101, the depth of opening 101 is reduced by the thickness of embedded conductor layer 6 and the aspect ratio of opening 101 is reduced by that much. Therefore, in forming the external connection terminal 4, as shown in FIG. GA, the distance of solder ball 4′ and thin film conductor 5 is shortened. Also, by controlling the thickness of embedded conductor layer 6′, as shown in FIG. 6, solder ball 4′ can be in contact with thin film conductor 5. Accordingly, when reflowing the solder ball 4′, the defective connection between external connection terminal 4 and thin film conductor 5 and defective shape in external connection terminal 4 can be prevented.
However, in the conventional semiconductor devices, there is a problem caused by intermetallic compound layer 7′ generated at the interface of external connection terminal 4 and thin film conductor 5. The external connection terminal 4 is connected with wiring 2 through the intermetallic compound layer 7′ to be formed between external connection terminal 4 and thin film conductor 5 formed at the bottom of opening 101. Just after the external connection terminal 4 was formed, the intermetallic compound layer 7, of gold and tin-zinc alloy has a very thin thickness, as shown in FIG. 7A or 7B. However, when the semiconductor device is used as electronic parts (module) while being mounted on a mounting board, the intermetallic compound layer 7, as shown in FIG. 8A or 8B, grows and becomes thick since the interdiffusion between gold in thin film conductor 5 and tin-zinc alloy in external connection terminal 4 is promoted by a temperature rise in using the semiconductor device.
The intermetallic compound layer 7′ of gold and tin-zinc alloy is mechanically fragile. According as the thickness of intermetallic compound layer 7′ increases, as shown in FIG. 9A, cracks (CK) are likely to occur in the intermetallic compound layer 7′ due to thermal stress or mechanical stress in using the semiconductor device.
Further, if the semiconductor device is continuously used while having cracks in the intermetallic compound layer 7′, as shown in FIG. 9B, the intermetallic compound layer 7′ may be subject to breaking and the external connection terminal 4 may fall off the opening 101, i.e., the semiconductor device.
In order to prevent the falling-off of external connection terminal 4 caused by the growth of intermetallic compound layer 7′, a method is suggested that the opening 101 is masked using a masking tape so as not to form the thin film conductor 5 (gold plating) at the bottom of opening 101 (See Japanese patent application laid-open No. 2003-152032).
However, there is a problem that the steps of sticking the masking tape onto the wiring board before making the thin film conductor 5 and peeling it later are required. Therefore, the manufacturing cost of wiring board has to be increased by that much.